View Q67000-A9284-X201-K5_1513719.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p-dip-20-5 p-dso-20-1 high performance power combi controller tda 16888 semiconductor group 1 data sheet 1998-05-06 1overview 1.1 features pfc section C iec 1000-3 compliant C additional operation mode as auxiliary power supply C fast, soft switching totem pole gate drive (1 a) C dual loop control (average current and voltage sensing) C leading edge triggered pulse width modulation C peak current limitation C topologies of pfc preconverter are boost or flyback C continuous/discontinuous mode possible C 94% maximum duty cycle pwm section C improved current mode control C fast, soft switching totem pole gate drive (1 a) C soft-start management C trailing edge triggered pulse width modulation C topologies of pwm converter are feed forward or flyback C 50% maximum duty cycle to prevent transformer saturation C f pwm = f pfc t new type type ordering code package t tda 16888 Q67000-A9284-X201-K5 p-dip-20-5 t tda 16888g q67000-a9310-a702 p-dso-20-1
tda 16888 semiconductor group 2 data sheet 1998-05-06 special features C high power factor Ctypical 50 m a start-up supply current C low quiescent current (15 ma) C undervoltage lockout with internal stand-by operation C internally synchronized fixed operating frequency ranging from 15 khz to 200 khz C external synchronization possible C shutdown of both outputs externally triggerable C peak current limitation C overvoltage protection C average current sensing by noise filtering 1.2 general remarks the tda 16888 comprises the complete control for power factor controlled switched mode power supplies. with its pfc and pwm section being internally synchronized, it applies for off-line converters with input voltages ranging from 90 v to 270 v. while the preferred topologies of the pfc preconverter are boost or flyback, the pwm section can be designed as forward or flyback converter. in order to achieve minimal line current gaps the maximum duty cycle of the pfc is about 94%. the maximum duty cycle of the pwm, however, is limited to 50% to prevent transformer saturation.
tda 16888 semiconductor group 3 data sheet 1998-05-06 figure 1 pin configuration (top view) pfc cl gnd pfc out sync pwm ss pwm in v rosc pfc vc pfc vs aux vs ref pwm rmp 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 aep02461 pfc cc pfc cs pwm out pwm cs pfc iac 11 10 gnd s cc v pfc fb aep02486 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 v cc gnd s pfc iac pwm out pfc cs pfc cc ref v pfc out gnd pfc cl pfc fb pwm cs pwm rmp aux vs pfc vs pfc vc rosc pwm in pwm ss sync p-dso-20-1 p-dip-20-5
tda 16888 semiconductor group 4 data sheet 1998-05-06 1.3 pin definitions and functions pin no. symbol function 1 pfc iac ac line voltage sensing input 2 v ref 7.5 v reference 3 pfc cc pfc current loop compensation 4 pfc cs pfc current sense 5 gnd s ground sensing input 6 pfc cl sensing input for pfc current limitation 7 gnd ground 8 pfc out pfc driver output 9 v cc supply voltage 10 pwm out pwm driver output 11 pwm cs pwm current sense 12 sync oscillator synchronization input 13 pwm ss pwm soft-start 14 pwm in pwm output voltage sensing input 15 pwm rmp pwm voltage ramp 16 rosc oscillator frequency set-up 17 pfc fb pfc voltage loop feedback 18 pfc vc pfc voltage loop compensation 19 pfc vs pfc output voltage sensing input 20 aux vs auxiliary power supply voltage sense
tda 16888 semiconductor group 5 data sheet 1998-05-06 1.4 block diagram figure 2 aeb02357 5 v _ + 1.2 v d1 d2 5 v d3 d4 & 5.5 v 1 v 4 v & 6 v 5.5 v & & 0.4 v c10 10 k 1.5 v osc 0.45 v 1 6 v 7.4 v undervoltage lockout 11 v-14 v power management 7.5 v (output disable) voltage reference z3 17.5 v pwm bias control ota3 ota1 r s r s 17 pfc 18 4 vs 20 aux s 5 gnd cc 3 pfc vs 19 pfc cl 6 pfc 9 out pfc v 2 sync 12 rosc 16 pwm 13 ss in pwm 14 rmp pwm 15 cs pwm 11 gnd 7 out pwm fb vc pfc pfc cs iac pfc 1 8 10 ref cc v r 2 10 k w op1 1 m m 2 3 m q m op2 c1 ota2 c4 c2 c6 c3 1 v ff1 z1 v s v s s v _ < 30 m a c5 0.4 v 1 c9 op3 5 w r 1 v 1 r 3 100 k w v s z2 ff2 c7 c8 i 1 1 v _ + _ + _ + _ + _ + _ + + _ _ + + _ _ + _ + _ + _ + + _
tda 16888 semiconductor group 6 data sheet 1998-05-06 2 functional description power supply the tda 16888 is protected against overvoltages typically above 17.5 v by an internal zener diode z3 at pin 9 ( v cc ) and against electrostatic discharging at any pin by special esd circuitry. by means of its power management the tda 16888 will switch from internal stand-by, which is characterized by negligible current consumption, to operation mode as soon as a supply voltage threshold of 14 v at pin 9 ( v cc ) is exceeded. to avoid uncontrolled ringing at switch-over an undervoltage lockout is implemented, which will cause the power management to switch from operation mode to internal stand-by as soon as the supply voltage falls below a threshold of 11 v. therefore, even if the supply voltage will fall below 14 v, operation mode will be maintained as long as the supply voltage is well above 11 v. as soon as the supply voltage has stabilized, which is determined by the tda 16888s power management and its soft-start feature at pin 13 (pwm ss), the pwm section will be enabled by means of its internal bias control. protection circuitry both pfc and pwm section are equipped with a fast overvoltage protection (c6) sensing at pin 19 (pfc vs), which when being activated will immediately shut down both gate drives. in addition to improve the pfc sections load regulation it uses a fast but soft overvoltage protection (ota2) prior to the one described above, which when being activated will cause a well controlled throttling of the multiplier output q m . in case an undervoltage of the pfc output voltage is detected at pin 19 (pfc vs) by comparator c4 the gate drive of the pwm section will be shut down in order to reduce the load current and to increase the pfc output voltage. this undervoltage shutdown has to be prior to the undervoltage lockout of the internal power management and therefore has to be bound to a threshold voltage at pin 9 ( v cc ) well above 11 v. in order to prevent the external circuitry from destruction the pfc output pfc out (pin 8) will immediately be switched off by comparator c2, if the voltage at pin 19 (pfc vs) drops to ground caused by a broken wire. in a similar way measures are taken to handle a broken wire at any other pin in order to ensure a safe operation of the ic and its adjoining circuitry. if necessary both outputs, pfc out (pin 8) and pwm out (pin 10), can be shutdown on external request. this is accomplished by shorting the external reference voltage at pin 2 ( v ref ) to ground. to protect the external reference, it is equipped with a foldback characteristic, which will cut down the output current when v ref (pin 2) is shorted (see figure 4 ).
tda 16888 semiconductor group 7 data sheet 1998-05-06 both pfc and pwm section are equipped with a peak current limitation, which is realized by the comparators c3 and c9 sensing at pin 6 (pfc cl) and pin 11 (pwm cs) respectively. when being activated this current limitation will immediately shut down the respective gate drive pfc out (pin 8) or pwm out (pin 10). finally each pin is protected against electrostatic discharge. oscillator/synchronization the pfc and pwm clock signals as well as the pfc voltage ramp are synchronized by the internal oscillator (see figure 18 ). the oscillators frequency is set by an external resistor connected to pin 16 (rosc) and ground (see figure 5 ). the corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. in order to ensure superior precision of the clock frequency, the clock signal clk osc is derived from a triangular instead of a saw-tooth signal. furthermore to provide a clock reference clk out with exactly 50% duty cycle, the frequency of the oscillators clock signal clk osc is halved by a d-latch before being fed into the pfc and pwm section respectively (see figure 18 ). the ramp signal of the pfc section v pfc rmp is composed of a slowly falling and a steeply rising edge. this ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (gnd s) and for external compensation of op2 by means of pin 5 (gnd s) and pin 3 (pfc cc). the oscillator can be synchronized with an external clock signal supplied at pin 12 (sync). however, since the oscillators frequency is halved before being fed into the pfc and pwm section, a synchronization frequency being twice the operating frequency is recommended. as long as the synchronization signal is h the oscillators triangular signal v osc is interrupted and its clock signal clk osc is h (see figure 19 and figure 20 ). however, as soon as the external clock changes from h to l the oscillator is released. correspondingly, by means of an external clock signal supplied at pin 12 (sync) the oscillator frequency f osc set by an external resistor at pin 16 (rosc) can be varied on principle only within the range from 0.66 f osc to 2 f osc . if the oscillator has to be synchronized over a wider frequency range, a synchronization by means of the sink current at pin 16 (rosc) has to be preferred to a synchronization by means of pin 12 (sync). anyhow, please note, that pin 12 (sync) is not meant to permanently shutdown both pfc and pwm section. it can be used to halt the oscillator freezing the prevailing state of both drivers but does not allow to automatically shut them down. a shutdown can be achieved by shorting pin 2 ( v ref ) to ground, instead. finally, in order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (pwm ss) is less than 0.4 v (disabled pwm section).
tda 16888 semiconductor group 8 data sheet 1998-05-06 pfc section at normal operation the pfc section operates with dual loop control. an inner loop, which includes op2, c1, ff1 and the pfcs driver, controls the shape of the line current by average current control enabling either continuous or discontinuous operation. by the outer loop, which is supported by op1, the multiplier, op2, c1, ff1 and the pfc's driver, the pfc output voltage is controlled. furthermore there is a third control loop composed of ota1, op2, c1, ff1 and the pfcs driver, which allows the pfc section to be operated as an auxiliary power supply even when the pwm section is disabled. with disabled pwm section, however, the pfc section is operated with half of its nominal operating frequency in order to reduce the overall current consumption. based on a pulse-width-modulation, which is leading edge triggered with respect to the internal clock reference clk out and which is trailing edge modulated according to the pfc ramp signal v pfc rmp and the output voltage of op2 v pfc cc (see figure 18 ), the pfc section is designed for a maximum duty cycle of ca. 94% to achieve minimal line current gaps. pwm section the pwm section is equipped with improved current mode control containing effective slope compensation as well as enhanced spike suppression in contrast to the commonly used leading edge current blanking. this is achieved by the chain of operational amplifier op3, voltage source v 1 and the 1st order low pass filter composed of r 1 and an external capacitor, which is connected to pin 15 (pwm rmp). for crosstalk suppression between pfc and pwm section a signal-to-noise ratio comparable to voltage mode controlled pwms is set by operational amplifier op3 performing a fivefold amplification of the pwm load current, which is sensed by an external shunt resistor. in order to simultaneously perform effective slope compensation and to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of v 1 and finally fed into the 1st order low pass filter. the peak ramp voltage, that in this way can be reached, amounts to ca. 6.5 v. by combination of voltage source v 1 and the following low pass filter a basic ramp (step response) with a leading notch is created, which will fully compensate a leading spike (see figure 12 ) provided, the external capacitor at pin 15 (pwm rmp) and the external current sensing shunt resistor are scaled properly.
tda 16888 semiconductor group 9 data sheet 1998-05-06 the pulse-width-modulation of the pwm section is trailing edge modulated according to the pwm ramp signal v pwm rmp at pin 15 (pwm rmp) and the input voltage v pwm in at pin 14 (pwm in) (see figure 18 ). in contrast to the pfc section, however, the pulse- width-modulation of the pwm section is trailing edge triggered with respect to the internal clock reference clk out in order to avoid undesirable electromagnetic interference of both sections. moreover the maximum duty cycle of the pwm is limited to 50% to prevent transformer saturation. by means of the above mentioned improved current mode control a stable pulse-width- modulation from maximum load down to no load is achieved. finally, in case of no load conditions the pwm section may as well be disabled by shorting pin 13 (pwm ss) to ground.
tda 16888 semiconductor group 10 data sheet 1998-05-06 3 functional block description gate drive both pfc and pwm section use fast totem pole gate drives at pin 8 (pfc out) and pin 10 (pwm out) respectively, which are designed to avoid cross conduction currents and which are equipped with zener diodes (z1, z2) in order to improve the control of the attached power transistors as well as to protect them against undesirable gate overvoltages. at voltages below the undervoltage lockout threshold these gate drives are active low. in order to keep the switching losses of the involved power diodes low and to minimize electromagnetic emissions, both gate drives are optimized for soft switching operation. this is achieved by a novel slope control of the rising edge at each driver's output (see figure 13 ). oscillator the tda 16888s clock signals as well as the pfc voltage ramp are provided by the internal oscillator. the oscillators frequency is set by an external resistor connected to pin 16 (rosc) and ground (see figure 5 ). the corresponding capacitor, however, is integrated to guarantee a low current consumption and a high resistance against electromagnetic interferences. in order to ensure superior precision of the clock frequency, the clock signal clk osc is derived from the minima and maxima of a triangular instead of a saw-tooth signal (see figure 18 ). furthermore, to provide a clock reference clk out with exactly 50% duty cycle, the frequency of the oscillators clock signal clk osc is halved by a d-latch before being fed into the pfc and pwm section respectively. the ramp signal of the pfc section v pfc rmp is composed of a slowly falling and a steeply rising edge, the latter of which is triggered by the rising edge of the clock reference clk out. this ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (gnd s) and for external compensation of op2 by means of pin 5 (gnd s) and pin 3 (pfc cc). the slope of the falling edge, which in conjunction with the output of op2 controls the pulse- width-modulation of the pfc output signal v pfc out , is derived from the current set by the external resistor at pin 16 (rosc). in this way a constant amplitude of the ramp signal (ca. 4.5 v) is ensured. in contrast, the slope of the rising edge, which marks the minimum blanking interval and therefore limits the maximum duty cycle t on,max of the pfc output signal, is determined by an internal current source. in contrast to the pfc section the ramp signal of the pwm section is trailing edge triggered with respect to the internal clock reference clk out to avoid undesirable electromagnetic interference of both sections. moreover, the maximum duty cycle of the pwm is limited by the rising edge of the clock reference clk out to 50% to prevent transformer saturation.
tda 16888 semiconductor group 11 data sheet 1998-05-06 the oscillator can be synchronized with an external clock signal supplied at pin 12 (sync). as long as this clock signal is h the oscillators triangular signal v osc is interrupted and its clock signal clk osc is h (see figure 19 and figure 20 ). however, as soon as the external clock changes from h to l the oscillator is released. correspondingly, by means of an external clock signal supplied at pin 12 (sync) the oscillator frequency f osc set by an external resistor at pin 16 (rosc) can be varied on principle only within the range from 0.66 f osc to 2 f osc . please note, that the slope of the falling edge of the pfc ramp is not influenced by the synchronization frequency. instead the lower voltage peak is modulated. consequently, on the one hand at high synchronization frequencies f sync > f osc the amplitude of the ramp signal and correspondingly its signal-to-noise ratio is decreased (see figure 19 ). on the other hand at low synchronization frequencies f sync < f osc the lower voltage peak is clamped to the minimum ramp voltage (typ. 1.1 v), that at least can be achieved (see figure 20 ), which may cause undefined pfc duty cycles as the voltage v pfc cc at pin 3 (pfc cc) drops below this threshold. however, if the oscillator has to be synchronized over a wide frequency range, a synchronization by means of the sink current at pin 16 (rosc) has to be preferred to a synchronization by means of pin 12 (sync). in order to reduce the overall current consumption under low load conditions, the oscillator frequency itself is halved as long as the voltage at pin 13 (pwm ss) is less than 0.4 v (disabled pwm section). multiplier the multiplier serves to provide the controlled current i qm by combination of the shape of the sinusoidal input current i m1 derived from the voltage at pin 1 (pfc iac) by means of the 10 k w resistor r 2 , the magnitude of the pfc output voltage v m2 given at pin 18 (pfc vc) and the possibility for soft overvoltage protection v m3 (see chapter protection circuitry ). by means of this current the required power factor as well as the magnitude of the pfc output voltage is ensured. to achieve an excellent performance over a wide range of output power and input voltage, the input voltage v m2 is amplified by an exponential function before being fed into the multiplier (see figure 8 ). voltage amplifier op1 being part of the outer loop the error amplifier op1 controls the magnitude of the pfc output voltage by comparison of the pfc output voltage measured at pin 17 (pfc fb) with an internal reference voltage. the latter is fixed to 5 v in order to achieve immunity from external noise. to allow for individual feedback the output of op1 is connected to pin 18 (pfc vc).
tda 16888 semiconductor group 12 data sheet 1998-05-06 current amplifier op2 being part of the inner loop the error amplifier op2 controls the shape of the line current by comparison of the controlled current i qm with the measured average line current. this is achieved by setting the pulse width of the pfc gate drive in conjunction with the comparator c1. in order to limit the voltage range supplied at pin 4 (pfc cs) and at pin 5 (gnd s), clamping diodes d1, d2 and d3 are connected with these pins and ground. to allow for individual feedback the output of op2 is connected to pin 3 (pfc cc). ramp amplifier op3 for crosstalk suppression between pfc and pwm section a signal-to-noise ratio comparable to voltage mode controlled pwms is set by operational amplifier op3 performing a fivefold amplification of the pwm load current, which is sensed by an external shunt resistor. in order to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of v 1 and finally fed into a 1st order low pass filter. by combination of voltage source v 1 and the following low pass filter a step response with a leading notch is created, which will fully compensate a leading spike (see figure 12 ) provided, the external capacitor at pin 15 (pwm rmp) and the external current sensing shunt resistor are scaled properly. operational transconductance amplifier ota1 the tda 16888s auxiliary power supply mode is controlled by the fast operational transconductance amplifier ota1. when under low load or no load conditions a voltage below 5 v is sensed at pin 20 (aux vs), it will start to superimpose its output on the output q m of the multiplier and in this way will replace the error amplifier op1 and the multiplier. at normal operation, however, when the voltage at pin 20 (aux vs) is well above 5 v, this operational transconductance amplifier is disabled. operational transconductance amplifier ota2 by means of the operational transconductance amplifier ota2 sensing at pin 19 (pfc vs) a fast but soft overvoltage protection of the pfc output voltage is achieved, which when being activated ( v pfc vs > 5.5 v) will cause a well controlled throttling of the multiplier output q m (see figure 9 ). operational transconductance amplifier ota3 in order to achieve offset compensation of error amplifier op2 under low load conditions, that will not suffice to start ota1, the operational transconductance amplifier ota3 is introduced. it will start operation as soon as these conditions are reached, i.e. the voltage at pin 18 (pfc vc) falls below 1.2 v.
tda 16888 semiconductor group 13 data sheet 1998-05-06 comparator c1 the comparator c1 serves to adjust the duty cycle of the pfc gate drive. this is achieved by comparison of the output voltage of op2 given at pin 3 (pfc cc) and the voltage ramp of the oscillator. comparator c2 the comparator c2 serves to prevent the external circuitry from destruction by immediately switching the pfc output pfc out (pin 8) off, if the voltage at pin 19 (pfc vs) drops below 1 v due to a broken wire. comparator c3 by means of this extremely fast comparator sensing at pin 6 (pfc cl) peak current limitation is realized. when being activated ( v pfc cl < 1 v) it will immediately shut down the gate drive of the pfc section (pin 8, pfc out). in order to protect c3 against undervoltages at pin 6 (pfc cl) due to large inrush currents, this pin is equipped with an additional clamping diode d4. comparator c4 this comparator along with the tda 16888s power management serves to reset the pwm sections soft start at pin 13 (pwm ss). c4 becomes active as soon as an undervoltage ( v pfc vs < 4 v) of the pfc output voltage is sensed at pin 19 (pfc vs). comparator c5 based on the status of the pwm sections soft start at pin 13 (pwm ss), the comparator c5 controls the bias of the entire pwm section. in this way the pwm section is switched off giving a very low quiescent current, until its soft start is released. comparator c6 overvoltage protection of the pwm sections input voltage sensed at pin 19 (pfc vs) is realized by comparator c6, which when being activated will immediately shut down both gate drives pfc out (pin 8) and pwm out (pin 10). comparator c7 this comparator sensing at pin 13 (pwm ss) and at pin 15 (pwm rmp) controls the pulse width modulation of the pwm section during the soft start. this is done right after the pwm section is biased by comparator c5.
tda 16888 semiconductor group 14 data sheet 1998-05-06 comparator c8 the control of the pulse width modulation of the pwm section is taken over by comparator c8 as soon as the soft start is finished. this is achieved by comparison of the pwm output voltage at pin 14 (pwm in) and the pwm voltage ramp at pin 15 (pwm rmp). comparator c9 by means of this extremely fast comparator sensing at pin 11 (pwm cs) peak current limitation is realized. when being activated ( v pwm cs > 1 v) it will immediately shut down the gate drive of the pwm section (pwm out). comparator c10 by means of the threshold of 0.4 v the comparator c10 allows the pwm duty cycle to be continuously controlled from 0 to 50%. as long as the ramp voltage at pin 15 (pwm rmp) is below this threshold the gate drive of the pwm section (pin 10, pwm out) is turned off.
tda 16888 semiconductor group 15 data sheet 1998-05-06 4 electrical characteristics 4.1 absolute maximum ratings t a = C 25 to 85 c parameter# symbol limit values unit remarks min. max. v cc supply voltage v s C0.3 v z3 v v z3 = zener voltage of z3 zener current of z3 i z3 C50maC v ref voltage v vref C 0.3 8 v v vref < v s rosc voltage v rosc C 0.3 8 v v rosc < v s sync voltage v sync C 0.3 8 v C pfc fb voltage v pfc fb C 0.3 8 v C pfc iac voltage v pfc iac C 0.3 15 v C aux vs voltage v aux vs C 0.3 8 v C pfc vs voltage v pfc vs C 0.3 8 v | i pfc vs |<1ma pfc cl voltage v pfc cl C 0.3 3 v C pwm ss voltage v pwm ss C 0.3 8 v v pwm ss < v vref pwm in voltage v pwm in C 0.3 8 v C pwm rmp voltage v pwm rmp C 0.3 8 v v pwm rmp < v vref pwm cs voltage v pwm cs C 0.3 3 v C pfc vc voltage v pfc vc C 0.3 8 v C pfc vc current i pfc vc C 20 20 ma C pfc cs current i pfc cs C 5 5 ma C gnd s current i gnd s C 5 5 ma C pfc cc voltage v pfc cc C 0.3 8 v C pfc cc current i pfc cc C 20 20 ma C pfc/pwm out dc current i out C 100 100 ma C pfc/pwm out peak clamping current i out C200ma v out =high pfc/pwm out peak clamping current i out C500 C ma v out = low junction temperature t j C40 150 cC
tda 16888 semiconductor group 16 data sheet 1998-05-06 note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. to avoid destruction make sure, that for any pin except for pins pfc out and pwm out the currents caused by transient processes stay well below 100 ma. for the same reason make sure, that any capacitor that will be connected to pin 9 ( v cc ) is discharged before assembling the application circuit. in order to characterize the gate drivers output performance figure 14 , figure 15 , figure 16 and figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. note: within the operating range the ic operates as described in the functional description. in order to characterize the gate drivers output performance figure 14 , figure 15 , figure 16 and figure 17 are provided, instead of referring just to a single parameter like the maximum gate charge or the maximum output energy. storage temperature t s C65 150 cC thermal resistance r thja C 60 k/w p-dip-20-5 thermal resistance r thja C70k/wp-dso-20-1 4.2 operating range parameter symbol limit values unit remarks min. max. v cc supply voltage v s 0 v z3 v v z3 = zener voltage of z3 zener current i z3 0 50 ma limited by t j,max pfc/pwm out current i out C1 1.5 a C pfc iac input current i pfc iac 01maC pfc/pwm frequency f out 15 200 khz C junction temperature t j C25 125 cC 4.1 absolute maximum ratings (contd) t a = C 25 to 85 c parameter# symbol limit values unit remarks min. max.
tda 16888 semiconductor group 17 data sheet 1998-05-06 4.3 characteristics note: the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range t a from C 25 c to 85 c typical values represent the median values, which are related to production processes. if not otherwise stated, a supply voltage of v s =15v is assumed. 1) see figure 3 2) design characteristics (not meant for production testing) supply section parameter symbol limit values unit test condition min. typ. max. zener voltage 1) v z3 16.0 17.5 19.0 v i z3 =30ma zener current i z3 CC500 m a v s 15.5 v 2) quiescent supply current i s CC12ma v pwm ss =0v r rosc =51k w c l =0v pfc enabled pwm disabled CC15ma v pwm ss =6v r rosc =51k w c l =0f pfc enabled pwm enabled supply current i s CC40ma v pwm ss =6v r rosc =51k w c l =4.7nf pfc enabled pwm enabled
tda 16888 semiconductor group 18 data sheet 1998-05-06 1) see figure 3 2) to ensure the voltage fallback of pin pfc cl is disabled. undervoltage lockout parameter symbol limit values unit test condition min. typ. max. power up, rising voltage threshold 1) v s,up 13.0 14.0 14.5 v C power down, falling voltage threshold 1) v s,dwn 10.5 11.0 11.5 v C power up, threshold current i s,up C 23 100 m a v s = v s,up C0.1v v pfc cl <0.3v 2) stand-by mode internal voltage reference parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 4.9 5.0 5.1 v measured at pin pfc vc line regulation d v ref CC40mv d v s =3v
tda 16888 semiconductor group 19 data sheet 1998-05-06 1) see figure 4 2) design characteristics (not meant for production testing) 3) transient reference value 1) see figure 5 external voltage reference parameter symbol limit values unit test condition min. typ. max. buffered output voltage v vref 7.2 7.5 7.8 v C3ma i vref 0 line regulation d v vref CC50mv d v s =3v load regulation d v vref 040100mv d i vref =2ma maximum output current 1) i vref C10C6C4ma v vref =6.5v short circuit current 1) i vref CC2Cma v vref =0v shutdown hysteresis, rising voltage threshold v vref C6.6CvC shutdown hysteresis, falling voltage threshold v vref C6.2Cv C shutdown delay t d,vref C500Cns v vref =5v 2)3) v pfc out =3v 2)3) v pwm out =3v 2)3) oscillator parameter symbol limit values unit test condition min. typ. max. pfc/pwm frequency 1) f out50 43 50 57 khz r rosc =110k w pfc/pwm frequency 1) f out100 87 100 113 khz r rosc =51k w pfc/pwm frequency, line regulation d f out CC1% d v s =3v r rosc =51k w maximum ramp voltage v pfc rmp 5.0 5.4 5.6 v C minimum ramp voltage v pfc rmp 0.8 1.1 1.4 v C sync, low level voltage v sync CC0.4v C sync, high level voltage v sync 3.5 C v vref vC sync, input current i sync CC20 m a v sync <0.4v C C 150 m a v sync =3.5v
tda 16888 semiconductor group 20 data sheet 1998-05-06 1) see figure 6 2) see figure 9 3) transient reference value 4) design characteristics (not meant for production testing) pfc section parameter symbol limit values unit test condition min. typ. max. max duty cycle 1) d on,pfc 91 94 98 % v pfc out =2v 3) r rosc =51k w c l =4.7nf multiplier throttling (ota2), threshold voltage 2) v pfc vs 5.25.55.8v 0.9 i pfc cs i pfc iac = 100 m a v pfc vc =6v ota1 disabled overvoltage protection (c6), rising voltage threshold v pfc vs 5.86 6.2v C overvoltage protection (c6), falling voltage threshold v pfc vs 5.35.55.7v C overvoltage protection (c6), turn-off delay t d,ov C2C m s v pfc vs =6.5v 3)4) v pfc out =3v 3)4) broken wire detection (c2), threshold voltage v pfc vs 0.93 1 1.07 v C voltage sense, input current i pfc vs 0.2 0.45 0.7 m a v pfc vs =1v current limitation (c3), threshold voltage v pfc cl 0.93 1 1.07 v C current limitation (c3), input current i pfc cl 1C10 m a v pfc cl =1v current limitation (c3, d4), clamping voltage v pfc cl C 0.9 C C 0.1 v i pfc cl =C500 m a current limitation (c3), turn-off delay t d,cl 30 C 150 ns v pfc cl =0.75v 3) v pfc out =3v 3) c l =4.7nf
tda 16888 semiconductor group 21 data sheet 1998-05-06 1) design characteristics (not meant for production testing) 2) for input voltages below this threshold the multiplier output current remains constant. for input voltages above this threshold the output rises exponentially (see figure 8 ). 3) see figure 7 multiplier parameter symbol limit values unit test condition min. typ. max. input current i pfc iac 0 C1maC input voltage v pfc vc 0C6.7vC exponential function, threshold voltage v pfc vc C1.1Cv 1)2) maximum output current i pfc cs C 320 C 420 C 550 m a ota1 disabled output current 3) i pfc cs C C 100 C 500 na i pfc iac =0a v pfc vc =2v ota1 disabled CC 1.2C m a i pfc iac =25 m a v pfc vc =2v ota1 disabled CC 10C m a i pfc iac =25 m a v pfc vc =4v ota1 disabled CC 40C m a i pfc iac =100 m a v pfc vc = 4 v ota1 disabled CC 150C m a i pfc iac =400 m a v pfc vc =4v ota1 disabled CC 170C m a i pfc iac =100 m a v pfc vc =6v ota1 disabled
tda 16888 semiconductor group 22 data sheet 1998-05-06 1) for input voltages below this threshold the output current is linearly increasing until at ca. 4.8 v the maximum output current is reached. 1) design characteristics (not meant for production testing) operational transconductance amplifier (ota1) parameter symbol limit values unit test condition min. typ. max. auxiliary power supply, threshold voltage 1) v aux vs 4.8 5.0 5.2 v i pfc cs =C1 m a multiplier disabled input current i aux vs C C15 m a v aux vs >5.2v C20 C C m a v aux vs <4.8v output current i pfc cs C0C m a v aux vs >5.2v 1) CC 30C m a v aux vs <4.8v operational transconductance amplifier (ota3) parameter symbol limit values unit test condition min. typ. max. offset compensation, threshold voltage v pfc vc 1.1 1.2 C v C input current i pfc vc C 1 C C m a 1) output current i gnd s C0C m a v pfc vc >1.2v CC10C m a v pfc vc <1.1v
tda 16888 semiconductor group 23 data sheet 1998-05-06 1) guaranteed by wafer test 2) design characteristics (not meant for production testing) voltage amplifier (op1) parameter symbol limit values unit test condition min. typ. max. offset voltage v off C4 C 4 mv 1) input current i pfc fb C1 C 1 m a v pfc fb =4v open loop gain a pfc vc C85Cdb 2) input voltage range v pfc fb 0C6vC voltage sense, threshold voltage v pfc fb 4.9 5 5.1 v C output, maximum voltage v pfc vc 6.3 C v vref v i pfc vc =C500 m a output, minimum voltage v pfc vc 0.5 C 1.1 v i pfc vc =500 m a output, short circuit source current i pfc vc CC10Cma v pfc vc =0v v pfc fb =4.9v output, short circuit sink current i pfc vc C10Cma v pfc vc =6.4v v pfc fb =5.1v
tda 16888 semiconductor group 24 data sheet 1998-05-06 1) design characteristics (not meant for production testing) current amplifier (op2) parameter symbol limit values unit test condition min. typ. max. offset voltage v off C5 C1 3 mv C input current i pfc cs i gnd s C 500 C 500 na C open loop gain a pfc cc C110CdbC gain bandwidth product f t C2.5Cmhz 1) phase margin j C60C 1) common mode voltage range v cmvr C0.2 C 0.5 v 1) clamped input voltage, upper threshold (d2, d3) v pfc cs v gnd s 0.4 C 1.0 v i pfc cs =500 m a i gnd s = 500 m a multiplier, ota1 and ota3 disabled clamped input voltage, lower threshold (d1) v pfc cs C0.9 C C0.1 v i pfc cs =C500 m a multiplier and ota1 disabled output, maximum voltage v pfc cc 6.3 C v vref v i pfc cc = C 500 m a output, minimum voltage v pfc cc 0.5 C 1.1 v i pfc cc =500 m a output, short circuit source current i pfc cc CC10Cma v pfc cc =0v v pfc cs =0v v gnd s =0.5v output, short circuit sink current i pfc cc C10Cma v pfc cc =6.5v v pfc cs =0.5v v gnd s =0v
tda 16888 semiconductor group 25 data sheet 1998-05-06 1) transient reference value pwm section parameter symbol limit values unit test condition min. typ. max. undervoltage protection (c4), threshold voltage v pfc vs 3.8 4.0 4.2 v C bias control (c5), rising voltage threshold v bc,th C0.45CvC bias control (c5), falling voltage threshold v bc,th C0.4CvC softstart ( i 1 ), charging current i i1 20 30 40 m aC softstart, maximum voltage v pwm ss C6.7CvC input voltage v pwm in 0.4 C 7.4 v C pwm in C gnd resistance r 3 75 100 150 k w C ramp (op3), voltage gain a op3 C5Cv/vC ramp (c10), pulse start threshold voltage v rmp 0.36 0.4 0.5 v C ramp, maximum voltage v rmp C6.5CvC ramp ( v 1 ), voltage offset v v1 C1.5CvC ramp ( r 1 ), output impedance z rmp C10Ck w C maximum duty cycle d on,pwm 41 C 50 % v pwm out =2v 1) r rosc =51k w c l =4.7nf current sense (c9), voltage threshold v cs,th 0.9 1.0 1.1 v C current sense (c9), overload turn-off delay t d,cs 30 C 250 ns v pwm cs =1.25v 1) v pwm out =3v 1) c l =4.7nf
tda 16888 semiconductor group 26 data sheet 1998-05-06 1) see figure 13 2) transient reference value 3) the gate drivers output performance is characterized in figure 14 , figure 15 , figure 16 and figure 17 . 4) design characteristics (not meant for production testing) gate drive (pwm and pfc section) parameter symbol limit values unit test condition min. typ. max. output, minimum voltage v out CC1.2vv s =5v i out =5ma CC1.5v v s =5v i out =20ma C0.8Cv i out =0a C1.62.0v i out =50ma C0.2 0.2 C v i out =C50ma output, maximum voltage v out 10 11 12 v v s =16v t h =10 m s c l =4.7nf 10.0 10.5 C v v s =12v t h =10 m s c l =4.7nf 8.8 C C v v s = v s,dwn +0.2v t h =10 m s c l =4.7nf rise time 1) t r C150Cns v out =2v8v 2) c l =4.7nf C100Cns v out =3v6v 2) c l =4.7nf fall time t f C30Cns v out =9v3v 2) c l =4.7nf C40Cns v out =9v2v 2) c l =4.7nf output current, rising edge 3) i out C1 C C a c l =4.7nf 4) output current, falling edge 3) i out CC1.5a c l =4.7nf 4)
tda 16888 semiconductor group 27 data sheet 1998-05-06 note: if not otherwise stated the figures shown in this section represent typical performance characteristics. figure 3 undervoltage lockout hysteresis and zener diode overvoltage protection figure 4 foldback characteristic of pin 2 ( v ref ) aed02462 v vcc vcc i s, up i s i v s, dwn v s, up z3 v aed02463 0 0 v vref vref i 1 2 3 4 5 6 7 8 -1 -2 -3 -4 -5 -6 ma -8 -7 v
tda 16888 semiconductor group 28 data sheet 1998-05-06 figure 5 pfc/pwm frequency figure 6 maximum pfc duty cycle aed02464 r osc out f k w 10 10 100 100 khz 400 500 aed02465 0 80 r osc on, pfc, max d 100 200 300 400 85 90 95 100 % k w
tda 16888 semiconductor group 29 data sheet 1998-05-06 figure 7 multiplier linearity figure 8 multiplier dynamic aed02466 0 0 i pfc iac pfc ccs i 0.2 0.4 0.6 0.8 1 100 200 300 400 500 m a ma 2 v 3 v 4 v 5 v 6 v = 7 v v pfc vc 0 0 v pfc vc pfc ccs i 100 200 300 400 500 m a 12 3 4 5 6 7 v pfc iac i m a = 800 a 400 m a 200 m a 100 m a 50 m a 25 m aed02356
tda 16888 semiconductor group 30 data sheet 1998-05-06 figure 9 multiplier throttling by ota2 figure 10 open loop gain and phase characteristic of voltage amplifier op1 5.0 0 v pfc vs pfc ccs i 100 200 300 400 500 m a pfc iac i m a > 300 a 250 m a 200 m a 150 m a 100 m a 50 m aed02467 5.25 5.5 5.75 6.0 v = 6 v v pfc vc 0 10 -2 pfc vc a frequency 20 40 60 80 100 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 aed02468 hz -150 -120 -90 -60 -30 0 pfc vc a f f db deg
tda 16888 semiconductor group 31 data sheet 1998-05-06 figure 11 open loop gain and phase characteristic of current amplifier op2 figure 12 pwm ramp composition scheme 0 10 -2 pfc cc a frequency 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 aed02469 hz -180 pfc cc a f f deg db 20 -150 40 -120 60 -90 80 -60 100 -30 120 0 aed02470 0 0 time pwm rmp v 0 t/2 t 1 v v 1 2 v 3 1 v 4 1 v 1 v /2 1 pwm cs v v pwmcs = 0
tda 16888 semiconductor group 32 data sheet 1998-05-06 figure 13 rising edge of driver output figure 14 power dissipation of single gate driver at f out =15khz aed02471 0 0 time pfc out v 0.1 0.2 0.3 0.4 2 4 6 8 10 12 v m s aed02542 0 0 d p 10 20 30 40 50 nf 50 100 150 mw c l r l = 0 w r l = 1 w r l = 2 w r l = 5 w r l = 10 w = 15 khz f out = 0.194 w p d0
tda 16888 semiconductor group 33 data sheet 1998-05-06 figure 15 power dissipation of single gate driver at f out =50khz figure 16 power dissipation of single gate driver at f out = 100 khz aed02543 0 0 d p 10 20 30 40 50 nf mw c l r l = 0 w r l = 1 w r l = 2 w r l = 5 w r l = 10 w = 50 khz f out = 0.197 w p d0 100 200 300 400 500 aed02544 0 0 d p 10 20 30 40 50 nf mw c l r l = 0 w r l = 1 w r l = 2 w r l = 5 w r l = 10 w = 100 khz f out = 0.201 w p d0 0.2 0.4 0.6 0.8 1
tda 16888 semiconductor group 34 data sheet 1998-05-06 figure 17 power dissipation of single gate driver at f out =200khz aed02545 0 0 d p 10 20 30 40 50 nf 0.5 1.0 1.5 mw c l r l = 0 w r l = 1 w r l = 2 w r l = 5 w r l = 10 w = 200 khz f out = 0.212 w p d0
tda 16888 semiconductor group 35 data sheet 1998-05-06 figure 18 timing diagram without synchronization aet02546 osc v clk osc pfc rmp v pfc out v pwm rmp v pwm out v clk out time on, max t on, max t v pwm in bc, th v v pfc cc
tda 16888 semiconductor group 36 data sheet 1998-05-06 figure 19 timing diagram with synchronization ( f sync > f osc ) aet02547 osc v clk osc pfc rmp v pfc out v pwm rmp v pwm out v clk out time on, max t on, max t v bc, th pwm in v v pfc cc sync v
tda 16888 semiconductor group 37 data sheet 1998-05-06 figure 20 timing diagram with synchronization ( f sync < f osc ) aet02548 osc v clk osc pfc rmp v pfc out v pwm rmp v pwm out v clk out time on, max t on, max t bc, th v v pwm in pfc cc v sync v
tda 16888 semiconductor group 38 data sheet 1998-05-06 5 package outlines p-dip-20-5 (plastic dual in-line package) gpd05587 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tda 16888 semiconductor group 39 data sheet 1998-05-06 110 11 20 index marking 1) does not include plastic or metal protrusions of 0.15 max per side 2) does not include dambar protrusion of 0.05 max per side gps05094 2.65 max 0.1 0.2 -0.1 2.45 -0.2 +0.15 0.35 1.27 2) 0.2 24x -0.2 7.6 1) 0.35 x 45? 0.23 8? max +0.09 +0.8 0.3 10.3 0.4 12.8 -0.2 1) p-dso-20-1 (plastic dual small outline) gps 05094 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

▲Up To Search▲

Price & Availability of Q67000-A9284-X201-K5

	To Download Q67000-A9284-X201-K5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .